SYMBOL CLOCK REPRODUCING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide the symbol clock reproducing circuit of π/4 shift QPSK modulation system not to degrade reception sensitivity even when a symbol clock deviated for ±1/2 symbol is reproduced. SOLUTION: Concerning this symbol clock reproducing circuit, a DPLL control part 13 is provided and a DPLL 12 is controlled so as to pull a regenerative symbol clock again after the phase of the regenerative symbol clock is shifted for +1/4 symbol at prescribed timing. The symbol clock can be reproduced for two samples per symbol and the circuit scale is reduced.