| 摘要 |
A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16). The edge termination structure includes a first well (34) of a first conductivity type underlying the polysilicon layer (26) and completely surrounding the active cells, a second well (30) of an opposite conductivity completely surrounding the first well (34), and metallization (42) contacting the second well (30). The first well (34) is part of a low-voltage ring (28) while the second well (30) is part of a high-voltage ring. The wells (30, 34) are preferably spaced relative to each other and to the device edge (48) to provide ballast resistance through the epitaxial layer (16), such that a breakdown will not be able to generate enough localized current to damage or destroy the device (100) when a reverse power pulse is experienced.
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