| 摘要 |
PROBLEM TO BE SOLVED: To generate a clock signal which is synchronized with a reference signal to be inputted and has a frequency other than the frequency of an integral multiple (or 1/integer) of the frequency of the reference signal. SOLUTION: This device is provided with a frequency dividing part 10 consisting of a phase calculation part 1, a sine calculation part 2 and a D/A conversion part 3 and with a low-pass filter(LPF) 4, and an output signal of the LPF 4 is supplied to a phase comparator 5. The phase calculation part 1 calculates a phase θ(nT) of a reference signal SREF in a generation timing t=nT (n indicates an integer, and T indicates a frequency of a clock signal SCL) of a clock signal SCL, by dividing the phase θ into an integer part and a decimal part and outputs the integer part as a digital phase value. The sine calculation part 2 converts the digital phase value into the amplitude of a sine wave signal, and its amplitude is D/A converted and is supplied to the phase comparator 5. |
