Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
摘要
A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
申请公布号
US5850105(A)
申请公布日期
1998.12.15
申请号
US19970822120
申请日期
1997.03.21
申请人
ADVANCED MICRO DEVICES, INC.
发明人
DAWSON, ROBERT;MICHAEL, MARK W.;BANDYOPADHYAY, BASAB;FULFORD, JR., H. JIM;HAUSE, FRED N.;BRENNAN, WILLIAM S.