| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to integrate on one and the same substrate a first insulating gate transistor wherein microminiature contact holes can be formed in gate electrodes by self alignment and a second insulating gate transistor wherein it is possible to prevent short channel effect and yet sufficiently relieve parasitic resistance in DRAM where a memory cell section is mounted together with a peripheral circuit section. SOLUTION: For example, a plurality of MOSFET's 20A are formed in the cell region 11a on a semiconductor substrate 11 in accordance with the minimum design rules and further a gate sidewall 22A of a sidewall insulating film 22a is formed on the sidewall of each gate electrode 21A. At least one MOSFET 20B is formed in a peripheral circuit region 11b, and gate sidewalls 22B of sidewall insulating films 22a, 22b are formed on the sidewalls of a gate electrode 21B. |
