发明名称 POWER-ON RESETTING CIRCUIT
摘要 <p>PURPOSE:To obtain the reset signal that continues for a certain time necessary for initial resetting, by resetting an FF in a certain time after installing the FF and an integral network in case the initialization reset signal is obtained to be used for a microcomputer. CONSTITUTION:The power source +Vcc is supplied to an integral network 1 consisting of a resistance R1 and a capacitor C1 and receives a waveform shaping through a Schmitt gate 2 and an inverter gate 3. The output of the shaped gate 3 is supplied to a terminal S formed with NOR gates 7 and 8. Then a power-on reset signal 13 is extracted out of the output of the gate 8 and at the same time supplied to an inverter gate 10. And the output of an integral network 11 comprising a resistance R2 and a capacitor C2 is supplied to the input of the terminal R of an FF9 after a waveform shaping received through a Schmitt gate 12. In such constitution, a signal 15 that continues for a certain time after a normal rise of the power source is obtained at the signal 13. Thus a hang-up can be prevented for a computer.</p>
申请公布号 JPS5717043(A) 申请公布日期 1982.01.28
申请号 JP19800090654 申请日期 1980.07.04
申请人 HITACHI LTD 发明人 SAKAI KATSUZOU
分类号 H03K17/22;G06F1/24;(IPC1-7):06F1/00 主分类号 H03K17/22
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