| 摘要 |
A high availability computer system and methodology including a backplane, having at least one backplane communication bus (208a-d) and a diagnostic bus (206), a plurality of motherboards (202a-h), each interfacing to the diagnostic bus (206). Each motherboard (202a-h) also includes a memory system (252) including main memory distributed among the plurality of motherboards (202a-h), at least one daughterboard (250a-b) and a scan chain that electrically interconnects functionalities mounted on each motherboard (202a h) and daughterboard (250a-b). The system including instructions and criteria to automatically test the functionalities and electrical connections, using the scan chain, to determine the presence of faulted components and to functionally remove the faulted components from the computer system. |
| 申请人 |
DATA GENERAL CORPORATION |
发明人 |
YEUNG, SIMON N.;HUCK, DAN R.;RADOGNA, TOM V.;HUNT, MICHAEL F.;GILLOTT, BARRY E.;GUYER, JAMES M.;VALENTINE, ROB P.;KIMMELL, JEFF S.;HEYDA, ANDREA;PIKE, ROB J.;SPORTER, MICHAEL;COX, JOSEPH;TRUEBENBACH, LIZ M.;KEATING, DAVID L.;GELINAS, ROBERT G.;ROUX, PHIL J.;WEILER, PAT J.;SHERMAN, ART A.;TUCKER, DOUG J.;BAXTER, WILLIAM F. |
