| 摘要 |
PROBLEM TO BE SOLVED: To establish the phase locked state at a high speed by detecting a deviation when a clock phase is deviated from a phase of a synchronizing signal input so as to correct a clock generating section with a correction quantity depending on the deviation. SOLUTION: In this phase locked loop consisting of a phase comparator 1 and a voltage controlled oscillator 3 or the like, an A/D converter 6 converts a voltage from a low pass filter 2 into a digital signal. A level half a prescribed output level of the A/D converter 6 is set to a reference level setting section 10 as a reference level and a comparator section 8 compares the input level from the A/D converter 6 with the reference level set by the reference level setting section 10. Control data to control a programmable multiplier in response to a difference between the reference level and the input level are stored in a storage section 9 and a control section 7 reads control data in response to the comparison result by the comparator section 8 from the storage section 9 to control the programmable multiplier 4. |
