Dual port memory having testing circuit

摘要

An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports. The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.