| 摘要 |
The invention is a power conserving clock driver circuit operative where a differential pair of clock (clock+ and clock-) signals are desired. The circuit responds to transitions in both clock signals to turn off the clock driver transistors (M1P,M1N) (M2N, M2P) for a period of time. During that period of time, a pass gate configuration (M3N, M3P) is conductive. When this occurs, the charge on one of the capacitive loads CL1 or CL2 is transferred through the inductor Lc. In this fashion, part of the charge on one of the capacitive loads is transferred directly to the other capacitive load thereby conserving power. The time period during which this power transfer occurs is the time for one half cycle at the natural resonant frequency of the circuit comprised of Lc, CL1 and CL2.
|
