| 摘要 |
PURPOSE:To realize high withstand voltage and high current capacity at a DMOS part being fabricated simultaneously by BiCMOS technology. CONSTITUTION:After a gate electrode 10 is formed on a channel ion implanted layer 8 formed on the surface of a P-well 5, a P-base region 21 is formed while being self-aligned by P-base forming process for bipolar transistor using the gate electrode 10 as a mask. A side wall 25 is then formed on the side face of the gate electrode 10 using the step for forming LDD structure in CMOS process and an N<+>-type source region 26NS is formed while being self-aligned by the step for forming the N<+>-type source-drain in CMOS process using the side wall 25 as a mask. Since the effective channel length is lengthened by the length (m) of side wall, the ratio of high concentration region is increased. Even if the channel ion implanted layer 8 is deficient in the total quantity of acceptor, the surface punch-through effect can be inhibited effectively because of ratio of the high concentration length thus realizing high withstand voltage and high current capacity. |
