| 摘要 |
<p>A frame buffer (17) including an array of memory cells (13), circuitry (11) for accessing the memory cells (13) to derive selected pixel data, and output circuitry (35) for providing data signals at an output port, the output circuitry (35) including circuitry (40) for determining the precise time required for a data signal to rise and fall at the output port, such circuitry (40) being selected to provide the minimum delay between succeeding data signals at the output port.</p> |
