| 摘要 |
PURPOSE: To provide the manufacturing method, wherein the occurrence of the bipolar effect in the field of a MOS transistor is avoided, and the vertical MOS transistor for reduction, which can perform the operation with less masks in the self-aligned pattern, is manufactured. CONSTITUTION: When a vertical MOS transistor is manufactured, the vertical layered constitution region doped for a drain 11, a well 3 and a source 4 are formed in a substrate 1. Under the state, wherein a Si3 N4 mask 5 is used for the surface of the substrate 1, the source 4 and a well 3 are cut, and a groove 6, which is closed self-aligningly with an insulating structure 8 by partial oxidation in the upper range, is etched. The insulating structure 8 protrudes to the side of the groove 6. Between the neighboring grooves 6 using the insurating structures as etching masks, a metalized part for connecting the source 4 and a well 3 is provided. A connecting hole 9 reaching the inside of the well 3 is opened.
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