发明名称 Process for manufacturing integrated circuits with very narrow electrodes
摘要 PCT No. PCT/FR92/00674 Sec. 371 Date Mar. 12, 1993 Sec. 102(e) Date Mar. 12, 1993 PCT Filed Jul. 10, 1992 PCT Pub. No. WO93/02470 PCT Pub. Date Feb. 4, 1993.A method for the manufacture of integrated circuits where it is desired to produce narrow conducting grids separated by a narrow gap and uses the lifting-up of silicon nitride (bird's bill) which is formed during a thick localized oxidation. A localized oxidation step is carried out and the oxide formed is totally removed. The edges (20, 22) of a nitride layer (14) stay overhanging. A conforming polycrystalline-silicon deposition enables silicon to be deposited uniformly, including beneath these edges. Finally, vertical anisotropic etching removes the silicon everywhere except beneath the overhanging edges, so that two silicon lines (28, 30) remain. An ion implantation (34) may be performed between the two lines. The method will find particular application for making anti-dazzle systems for photosensitive charge-coupled devices.
申请公布号 US5399525(A) 申请公布日期 1995.03.21
申请号 US19930030065 申请日期 1993.03.12
申请人 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES 发明人 BLANCHARD, PIERRE
分类号 H01L27/148;H01L21/285;H01L21/60;(IPC1-7):H01L21/441;H01L21/339 主分类号 H01L27/148
代理机构 代理人
主权项
地址