Analog delay circuit configuration

摘要

An analog delay circuit configuration includes a switching stage. A capacitor is connected upstream of the switching stage. A controlled current source has a current being definitive for a charging state of the capacitor. The current source is clocked with a pulse-to-interval ratio of less than 1. A current mirror configuration reduces the current of the current source. An inverter stage is coupled to the current mirror configuration and has an output side connected to the capacitor.