SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANT CELL TEST APPARATUS

摘要

The testing circuit providing checking means of the redundancy cells in a semiconductor memory device comprises a redundant column gate connecting the redundant memory cell and the data input/output lines; a redundant decoder generating address signals from the redundant test signals and the external address signals; a switching circuit receiving the redundant test signals and transferring the output signals of the redundant decoder to the redundant column gate.