| 摘要 |
<p>PURPOSE:To secure minimum clock high width without enlarging inter-clock delay rather than a certain maximum value even when this inter-clock delay is changed with the change of an operational condition such as the reduction of a power supply voltage or the like. CONSTITUTION:This circuit is provided with a delay circuit 3 to delay the clock in the (n-1)th phase order for prescribed time among multi-phase clocks phi1, phi2 and phi3, successively delaying the clock high width at the integed-fold rate 1 of a basic clock CL and delaying the phase at the integer-fold rate of the basic clock, AND circuit 4 to define the inversion of an output from the delay circuit 3 as one input and to define the clock in the n-th phase order as the other input, AND circuit 8 to define the inversion of the basic clock CL as one input and to define the n-th clock as the other input, and OR circuit 7 to define the outputs of the AND circuits 4 and 8 as the input.</p> |
