DIRECT MEMORY ACCESS INTERFACE FOR BUSES OF DIFFERENT WIDTH

摘要

An interface (10) is provided for regulating the transfer of data between a first device (14) having a data bus (26) of first width and a second device (12) having a bus (20) of second width. The interface (10) intercepts a first transfer request sent from the first device (14) and in response thereto the interface (10) generates emulating control signals of the second device (12) such that a first data of first width from the first device (14) is sent and intercepted in the interface (10). The interface (10) waits for the second data to arrive and the first data is passed together with the second data as a single data of the second width to the second device (12).