| 摘要 |
<p>PURPOSE:To reduce power consumption by eliminating the charging and discharging of an address line and a digit line within a period which is not concerned in an output signal. CONSTITUTION:Input signals 11-13 to input lines IL1-IL6 and the sampling timings of the inverted signals are controlled by an internal control signal IE. The internal control signal IE is the AND of a first clock signal C1 and a latch control signal E and also is the signal for latching the signals of the digit lines DL1-DL4.</p> |
