| 摘要 |
<p>PURPOSE:To provide the reset circuit of a multiprocessor system by which a reset can be exactly operated to the entire processors by the same clock phase, even when a jitter is included in a reset signal. CONSTITUTION:This circuit is equipped with plural holding circuits 36 and 37 which successively hold the reset signal outputted from a reset signal generating circuit 17 in a timing synchronizing with a clock signal outputted from a clock generating circuit 16, preparing means 40 and 41 which prepare signals indicating a prescribed period corresponding to the cycle of the clock signal by performing the logical operation of the outputs of the plural holding circuits 36 and 37, and stopping means 34 which stops the change of the polarity of the clock signal only in the period prepared by the preparing means 40 and 41.</p> |
