| 摘要 |
PURPOSE:To provide a vector processor capable of performing vector processing even when the dependency of definition/reference relation is present in subscript arrangement to perform indirect reference for list sum arithmetic operation, etc. CONSTITUTION:A register read/write control circuit 61 in the vector processor composed of plural vector registers 58-60, a vector computing element 62, a main storage device, and a cross-bar switch 57 to perform data transfer among those devices is provided with a designation means which uses data 67 in the vector register 58 outputted according to a readout designation address 70 for the vector register 58 as a readout designation address 71 and a write designation address 72 to the vector register 59. Thereby, it is possible to perform the vector processing even when the dependency of definition/reference relation exists in the subscript arrangement in an indirect reference vector arithmetic operation.
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