VERFAHREN ZUR EMPFAENGERSEITIGEN SYNCHRONISATION IN EINEM DIRECT-SEQUENCE-SPREAD-SPECTRUM-SYSTEM SOWIE ANORDNUNG HIERZU.

摘要

The limit of the count supply for the feedback signal in the coherent addition process is related by a specified inequality to the length of theperiods of the spread codes used. The arrangement includes a delay locked loop. Read-write memories (RAM) in conjunction with a circulating address counters act as delay devices in each loop of the coherent addition per spread code period. The address counters are set to the associated spread code periods.