发明名称 Method and apparatus for identifying manufacturing defects in solid state devices.
摘要 <p>A pattern inspection technique and apparatus, suitable for wafer and printed circuit board and related applications, employing novel intelligent imaged-pattern shrinking and expanding architecture to identify permissible line widths, spacings and in surrounding material context, and to identify defects or errors.</p>
申请公布号 EP0493657(A2) 申请公布日期 1992.07.08
申请号 EP19910117670 申请日期 1991.10.16
申请人 BELTRONICS, INC. 发明人 BISHOP, ROBERT;DAMON, RICHARD
分类号 G06T7/00 主分类号 G06T7/00
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