Clock pulse generator from basic clock signal - uses leading and lagging edge triggering technique and flip=flop stages to produce required clock pulse

摘要

The basic clock signal (SYSCLK) is fed to the input of an n-stage counter module (SK1). The circuit responds to both leading and lagging edges of the basic clock signal (SYSCLK) and clocks a 1 sequentially through the module which produces a primary clock output at each stage. A secondary circuit, consisting of logic gates and flip-flop stages, produces a range of clock pulses synchronised to the edges of the basic clock signal (SYSCLK). USE/ADVANTAGE - Esp. in semi-custom integrated circuits. Simple and reliable circuits.