| 摘要 |
<p>PURPOSE:To eliminate the need for tight delay adjustment and to use the circuit even when a clock frequency is changed by providing a 1st FF latching an input signal at the leading point of time of a clock signal, a 2nd FF latching the input signal at the trailing point of time, a selector and a control circuit. CONSTITUTION:A FF1 latches an input signal Din at the leading of a signal CLK and a FF2 latches the input signal at a leading of a signal inverse of CLK through an inverter 11. A selector 4 sends one designated signal in two latched inputs under the control of a control circuit 5 as an output signal Dout. When two change points or over exist in the input signal Din from the latch point of time of the clock signal CLK selected at present till the succeeding latch point of time, the change point of the Din and the leading of the clock selected by the selector 4 approach a same time and it is discriminated to be disable of accurate latch and the result latched by an inverted clock signal opposite to the clock signal selected at present is selected out and the result of latching the input Din accurately is outputted.</p> |
