| 摘要 |
<p>PURPOSE:To attain clock recovery at a reception section, to recover the original signal accurately, to avoid high signal speed, to simplify the circuit and to reduce the cost by inserting a low speed clock component to a data input signal. CONSTITUTION:A data input signal is supplied to an exclusive OR circuit 3 with a signal frequency-dividing at first a clock frequency at a 1st frequency divider circuit 4 by 1/n1 and the output is synchronized with a trigger signal from the leading and trailing of the clock frequency via a trigger circuit 6. Moreover, The output signal is supplied to an exclusive OR circuit 9 together with the clock frequency frequency-divided at a 2nd frequency divider circuit 10 by 1/n2 and the output signal is synchronized with the trigger signal the same as the signal of the pre-stage, and the signal synchronously with the original signal with lower clock frequency is generated, the signal is handled by a lower. frequency and the clock frequency is reproduced by a reception section 24 and the original signal is surely recovered. Thus, the clock recovery is attained by the reception section and the signal speed is not faster than the speed of the data signal, the circuit is simplified and the equipment is constituted with low cost general-purpose components.</p> |
