| 摘要 |
PURPOSE:To reduce the number of external terminal pins of an integrated circuit by supplying a data signal and a clock signal after multiplexing. CONSTITUTION:The circuit is the integrated circuit where a digital signal having a clock period and a data period in serial fashion is supplied, and it is provided with an input terminal pin P where the digital signal is inputted, a processing circuit provided with a data terminal D where the data signal in the data period is inputted and a clock terminal CK where the clock signal in the clock period is inputted, and a delay circuit DL which delays the clock signal to the data period and supplies it to the clock terminal CK. At such a case, the data of one channel can be fetched with one terminal. In such a manner, no terminal pin (p) for clock is required, thereby, the data as much on the channel can be fetched. |
