发明名称 Vertical phase adjust circuit.
摘要 <p>A vertical phase adjust circuit with high noise immunity for line locked surveillance cameras. To prevent noise from the AC line producing false output signals, a counter is used to lock out the delayed vertical line locked output signal. The horizontal scan frequency is counted from the time a vertical output is produced, and the vertical output signal is prevented until 98 percent of the period between legitimate vertical signals has elapsed. The circuit also includes a lock detect circuit to increase the time window during startup conditions to assure initial synchronization and an increased phase adjust range to permit synchronization with any other camera.</p>
申请公布号 EP0413468(A2) 申请公布日期 1991.02.20
申请号 EP19900308473 申请日期 1990.08.01
申请人 BURLE TECHNOLOGIES, INC. 发明人 RANDALL, JENNIFER L.
分类号 H03L7/00;H04N5/073;H04N5/232 主分类号 H03L7/00
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