发明名称 |
High speed numerical processor. |
摘要 |
Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48)(50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.
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申请公布号 |
EP0395240(A2) |
申请公布日期 |
1990.10.31 |
申请号 |
EP19900303654 |
申请日期 |
1990.04.05 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
STEISS, DONALD E.;HIPONA, MARIA B.;DARLEY, HENRY M. |
分类号 |
G06F7/537;G06F7/52;G06F7/53;G06F7/535;G06F7/552;G06F7/57 |
主分类号 |
G06F7/537 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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