发明名称 DEAD LOCK PHENOMENON PREVENTION CIRCUIT FOR PLL INCLUDING DIGITAL MIXER
摘要 PURPOSE:To eliminate the need for an externally mounted component and to reduce the cost by detecting that the value within absolute value symbols of fm=¦2fsc-NfM/2¦ is negative at a fault to close a gate so as to return to a normal lock point. CONSTITUTION:A deviation alpha deg. deviated from 2fsc inputting to 1st and 2nd mixers 10, 28 is not 90 deg., but a proper phase angle such as 270 deg., 45 deg., 225 deg.. Since a delay of 270 deg. is caused when fm' is positive and a delay of 90 deg. is caused when the fm' is negative, H, L of the fm fetched at the leading of the fm', that is, the Q output of a flip-flop 26 is L when the fm is positive and H when negative, then a gate 24 is opened at the L level, and closed at the H level, or the Q output of the flip-flop 26 is used to remain the gate 24 to be the AND gate as it is.
申请公布号 JPH02226913(A) 申请公布日期 1990.09.10
申请号 JP19890048182 申请日期 1989.02.28
申请人 FUJITSU LTD;FUJITSU VLSI LTD;MATSUSHITA ELECTRIC IND CO LTD 发明人 FUJII SHIGERU;IDO TAKAAKI;SHIMIZU MASAAKI;SUZUKI KEIJI;KONO TAKASHI
分类号 H04N5/06;H03L7/08;H03L7/095;H04N11/16 主分类号 H04N5/06
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