| 摘要 |
PURPOSE: To provide an integrated circuit having improved radiation hardening for suppressing the formation of a parasitic transistor, by arranging a pseudo gate on the thin oxide of high quality in a field region between mutually adjacent operation regions, arranging the dummy gate on the oxide, and biasing the dummy gate. CONSTITUTION: A thin layer 410 of the oxide of high quality is grown on a silicon substrate containing a region 200 becoming the operation region and a region 100 becoming the field region. A polysilicon plate layer 420 having conductivity is formed on the layer. Then, etching is executed and the region 200 becoming the operation region is exposed, a gate oxide layer 430 is grown and FET 300 and 325 are formed on the prescribed positions of the region 200 becoming the operation region. The polysilicon plate layer 420 is connected to a latent source terminal having prescribed size and polarity so that the formation of the parasitic transistor is suppressed in the region 100 becoming the field region by giving an electric field to the substrate by the polysilicon layer 420. Then, FET 300 and 325 are connected.
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