发明名称 LOGICAL OPERATION CIRCUIT
摘要 PURPOSE:To prevent the increase of a writing time by obtaining the AND and NOT of the arbitrary number of bits out of N bits without using a RAM, and obtaining OR several times from the result. CONSTITUTION:When a resetting signal the inverse of RST goes to true, the FF of an address counter 7 and a memory 6 is reset and an output goes to '0'. Here, the first address of a memory is read, a high order N bit of the data output of the memory goes to the input of the EXOR of an EXOR gate 1, the place designated to '1' is made into the input to the OR of an OR gate 2 while the polarity of an input signal b1, and for the place designated to '0', an input signal b1 is made into the input to the OR gate 2 as it is. The low order N bits of the data output of the memory goes to the input to the OR of the OR gate 2, the bit designated to '1' forcibly makes the output of the OR of the OR gate 2 into '1', the influence is not given to the AND operation of the other bit as the input of the AND of a next step 3, and only the bit designated to '0' goes to the effective input data bit of the AND of the next step 3. Thus, the writing time of the software can be shortened.
申请公布号 JPH01169624(A) 申请公布日期 1989.07.04
申请号 JP19870327017 申请日期 1987.12.25
申请人 HITACHI LTD 发明人 MASHITA TAMON
分类号 G06F7/04 主分类号 G06F7/04
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