| 摘要 |
PURPOSE:To suppress the generation of hot carriers and to decrease a short channel effect, by providing a low concentration, the same conductivity type impurity layer beneath a source region and a drain region. CONSTITUTION:On a p-type Si substrate, a gate insulating film 12, a gate electrode 13, a field insulating film 14, an n<+> type source region, an n<+> type drain region, an n<-> type source layer 17, an n<-> type drain layer 18 and an insulating film 19 are provided. Thus an embedded gate type FET is formed. Namely, a low concentration layer 17 and the layer 18 are provided in close proximity with the film 12 in this structure. The concentration of an electric field is alleviated in this structure, and the generation of hot carriers is suppressed. Since the low concentration layers are arranged on the side parts of the electrode 13 and the film 12, approaching of both low concentration layers due to heat treatment and the like becomes less. Therefore, the effective length of a channel becomes long, and a short channel effect is decreased. |
