| 摘要 |
PURPOSE:To omit an exclusive switch circuit and to shorten a gate delay time by setting an internal address signal at a latch circuit for external address signal as necessary and performing changeover between the external and internal address signals. CONSTITUTION:A switch means 104 inverts an external address signal via an inverter 104c and turns on and off a transmission gate 104a with control signals phi' and the inverse of phi' to set the external address signal at a latch circuit 1. Thus the external address signal is set under a latch state. The circuit 1 secures a loop connection between NAND gates 1a and 1b via an input terminal of one of both gates 1a and 1b. While the complementary refresh address setting signal RA1 and RA2 are inputted to the other input in a refresh state. In this case, the complementary signals phi and the inverse of phi' are set at 0 and 1 respectively so that both signals RA1 and RA2 can be set at the circuit 1. Thus the means 104 is turned off for separation of the external address signal. Then the address input is switched to a refresh address.
|
