| 摘要 |
Depletion-mode FET (13a of 8) joins to enhancement-mode FET (13b of 8) to store charge capacitively as a memory cell. That enhancement-mode FET (13b of 8) is connected to an FET capacitor (19). When the memory stores a high charge, a refresh clock pulse on a line (21), passes the capacitor (19), turns off enhancement-mode part of joined FETs (8), and is effective to gate refresh switch (25) on. When the memory stores ground, the capacitor (19) is not activated and does not pass the refresh pulses. The memory requires very low power for refresh, and is compact and practical for use in large arrays. |
