发明名称 MULTIPROCESSOR CONTROL SYSTEM
摘要 PURPOSE:To improve a processing speed and to reduce prefix areas on a main memory in a multiprocessor control system by using variably the prefix area of a system control processor on the main memory. CONSTITUTION:The processors IPU 20-22 having independent prefix areas 40-42 on a main memory 6 and prefix addresses corresponding to these areas 40-42 are stored in a fixed area 6-1. When either one of those IPUs gives a processing request to a system control processor SPU 23, the area 6-1 is retrieved by the SPU 23 and the prefix address of the IPU that had a processing request is set at a prefix register 27 as a prefix address of the SPU 23. Then the SPU 23 processes data on the prefix area of said IPU.
申请公布号 JPS63208971(A) 申请公布日期 1988.08.30
申请号 JP19870043546 申请日期 1987.02.25
申请人 FUJITSU LTD 发明人 KOYATA SHIGENORI;SAKURAI MITSUO;SATO NOBUYOSHI;KOMATSU TADAHIDE;NAKANO ICHIRO;HIRAI YOSHIRO
分类号 G06F15/16;G06F15/167;G06F15/177 主分类号 G06F15/16
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