| 摘要 |
PURPOSE:To decrease number of logic gates being components by applying a sampled input signal to a sequential comparison type A/D converter, writing data from a buffer into a RAM, bringing the impedance of a buffer into a high impedance, reading the data from the RAM and applying D/A conversion to the data for output. CONSTITUTION:An inputted sound signal is sampled by a sample-and-hold circuit 1. The sampled signal is converted into a digital signal through a sequential comparison type A/D converter comprising a comparator 2, a register 3 and a D/A converter 8 by making a buffer 5 into an active state (a state that an inputted signal is outputted as it is), and the output appears as an output of the register 3. A data A/D-converted is inputted to a data I/O of a RAM6 through a buffer 5 and written in an address designated by an address generation counter 7. The data written in the RAM6 is subject to same address designation by a counter 6 again after a prescribed period and then read. The readout data is inputted to the D/A converter 8, where the data is converted into an analog sound signal.
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