发明名称 INSTRUCTION PREFETCH CONTROL CIRCUIT
摘要 PURPOSE:To interrupt instruction and ristrict-to a minimum instruction fetch to go to wastel by an execution of a branch instruction by detecting the number of remaining bytes to be decoded constituting the branch instruction comparing it with the number of the bytes stored in an internal instruction buffer. CONSTITUTION:An instruction is inputted to a decoder 206 through an instruction bus 205 in sequence of fetched instructions. Output information from the decoder 206 is subtracted by one by a DEC 222 and inputted to a comparator 221 through a branch signal line 224. In a QC 216, the number of bytes stored in a queue 202 is calculated by a QRC 203 and a QWC 204 and the results is outputted to a comparator 221 through a queue status signal line 220. Information fed from the branch line 224 is compared with information fed from the queue status signal line 220 in the comparator 221. If the number of the bytes required for executing the branch instruction is all stored in the queue 202, a fetch interrupting signal line is made low level, as a result, an output line 219 of a two input AND 218 goes to low level and an interruption of the fetch is requested to a bus control 213.
申请公布号 JPS61211744(A) 申请公布日期 1986.09.19
申请号 JP19850053660 申请日期 1985.03.18
申请人 NEC CORP 发明人 KUWATA AKIRA
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
主权项
地址