发明名称 |
PARITY CHECK SYSTEM OF MICROPROGRAM STORAGE MEMORY |
摘要 |
PURPOSE:To shorten the processing time by generating addresses of a microprogram storage memory successively to read out a microprogram and performing parity check when specific information is sent from a central processing unit of a current system. CONSTITUTION:In case that a central processing unit 2 of a stand-by system is checked, a central processing unit 1 of the current system reads out control information from a main storage device 3 and sets it to a shift register 11. This information is set to a shift register 21 of the central processing unit 2 of the stand-by system. A sequence control part 26 starts the sequence of parity check when a parity check designating flip flop 25 is set. The sequence control part 26 outputs the microaddresses stored in a microprogram storage memory 27, and a parity check circuit 28 performs parity check of the outputted microprogram. |
申请公布号 |
JPS61161549(A) |
申请公布日期 |
1986.07.22 |
申请号 |
JP19850002721 |
申请日期 |
1985.01.11 |
申请人 |
FUJITSU LTD |
发明人 |
OSADA SATOSHI;SUGIYAMA HIROSHI |
分类号 |
G06F9/22;G06F11/10;G06F11/16 |
主分类号 |
G06F9/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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