| 摘要 |
PURPOSE:To reduce the area of a memory cell, to improve the degree of integration and to increase the speed of writing and reading by forming a drain or source region in a switching MISFET and a bit line connected to the region to a plane different from a surface to which a capacitance element is shaped. CONSTITUTION:An epitaxial growth layer 13 is formed onto a bit line 12 shaped to a diffusion layer in an silicon substrate 11, and the thickness of the layer 13 represents the gate length of a switching MISFET. An oxide film 14 mutually isolating memory cells is formed, and opening sections A as MISFETs are shaped to the growth layer 13 at central sections in several memory cell region. A capacitance element insulating film 15 as a gate insulating film, an MISFET gate insulating film 16 and a word line/bit line isolation insulating film 17 are shaped simultaneously, and a word line 18 consisting of a conductor electrode and a capacitance element electrode 19 as a conductor electrode are formed. Accordingly, the thick oxide film 14 mutually isolating the memory cells, the gate electrode for a capacitance element and the MISFETs can be arranged onto the surface of the substrate without clearances, thus reducing the areas of the memory cells. |
