| 摘要 |
PURPOSE:To realize high-speed timing operation with less power consumption, by operating a ring oscillating circuit when a low-speed clock signal and stopping it when the control signal of a counting circuit is inputted. CONSTITUTION:When the low-speed basic clock signal from a crystal oscillating circuit 1 changes from logic 1 to 0, FFs 13-16, and 18 are released from being in reset states. At the same time, the output of a logical circuit 19 changes from 1 to 0 and the ring oscillating circuit 2 outputs a high-speed clock pulse signal. Once counting 15 pulses of the high-speed clock signal, the counting circuit 3 outputs a signal to the signal input terminal D of the FF18. The FF18 stops the oscillating operation of the circuit 2 through an OR logical circuit 19. Therefore, the level of a clock signal output terminal 20 goes down to 0 and output signals -Q of the FFs 13-16, and 18 are held at 0, 0, 0, 0, and 1, respectively.Then when the output signal of the circuit 1 changes from 0 to 1, the FFs 13-16, and 18 are reset. Similarly, the high-speed clock pulse signal is outputted intermittently. |
