| 摘要 |
PURPOSE:To decrease the shift in phase, by detecting a point of time when a complex base power is maximum and controlling to which portion of an output waveform of a phase synchronizing oscilator the phase of a sampled clock is to be matched, for quickening the locking-in of the oscillated phase. CONSTITUTION:A complex base band signal after two-axis synchronizing detection is sampled in a frequency four times or its integral number of multiple of taht of a phase synchronizing oscillator 19 and enters a terminal 10. The input signal enters the 1st sampling circuit 21 with a delay for one clock period at a delay circuit 20 and is given to a square circuit 13. A signal sampled in a frequency CP2 twice the clock of a frequency division circuit 16 is calculated for the phase shift with the frequency CP1 four times the clock frequency and the phase of the oscillator 19 is controlled. The CP1 is a sampling clock of the 1st sampling circuit. The frequency divider is controlled with AND between a peak of an output of the square circuit 13 and a signal delaying a CDI signal. |
