| 摘要 |
PURPOSE:To improve the debugging efficiency of a simulator, by providing a margin for the condition interrupting a program during the execution of simulation in the simulator of a processor. CONSTITUTION:In the simulator of a processor, an upper and a lower limit addresses are registrated in a brake point address registration table BPTBL. When a program counter of a simulating processor or an execution address enters a section clipped with the upper and lower limit addresses of a table BPTBL, i.e., enters the brake area during the execution of simulation, the execution of simulation is interrupted. |
