发明名称 |
Programmable gain integrator stage including means for offset voltage elimination. |
摘要 |
<p>A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100,101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (Verror) is inverted and integrated one time for each integration of the input voltage (Vin), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (Vout).</p> |
申请公布号 |
EP0072741(A2) |
申请公布日期 |
1983.02.23 |
申请号 |
EP19820401498 |
申请日期 |
1982.08.06 |
申请人 |
AMERICAN MICROSYSTEMS, INCORPORATED |
发明人 |
HAGUE, YUSUF A.;SALETORE, VIKRAM;SCHULER, JEFFREY A. |
分类号 |
H03F3/34;G06G7/12;H03F1/30;H03F3/00;H03G3/00;H03K4/41;(IPC1-7):03G1/00;03F1/30;03F3/70 |
主分类号 |
H03F3/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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