| 摘要 |
<p>PURPOSE:To detect the leading of oscillation and a failure in oscillation level at the release of power down through the direct monitor of an oscillation level, by inputting an oscillator output to a gate circuit with different threshold level and collating the output of the gate circuit. CONSTITUTION:An output of an oscillator OSC is inputted to inverters (INV)G1 and G2. The threshold level of the INVG1 is set higher than that of the INVG2. The output of the INVG1 and G2 is inputted to a gate G3, and an output at a point (d) rises when the oscillating level is at the threshold level of the INVG1 or less and at that of the INVG2 or more, and whether or not the oscillation level is stable can directly be recognized by monitoring the output of the point (d). Thus, this system is used for the recognition of leading at down mode release for C-MOS LSI completely stopping an oscillator at the power down mode and used for the oscillation level at the oscillating state.</p> |
