| 摘要 |
PURPOSE:To execute the operation processing at a high speed, by providing a next address entry means, and a next address holding means for setting the head of the next address to be read out, on a data holding means, and selecting in order an operable instruction cell. CONSTITUTION:A data which is operated by plural instruction cells is held in an operand memory 19. In the memory 19, a data section 19-0, and a link address section 19-1 in which an address to be accessed next has been entered are provided. When a value transferred from an input updating part 7 is the second data and there is no idle queue for receiving a signal from an output port 18', a control part 22' enters the latest address that has been written in the memory 19, in a next address register 20. The address of the register 20 is read out by a link part 21, and an address of an operation cell having 2 operation executable values of the memory 19 is written in the memory 19. When there is an idle queue and an output has been requested, said address written in the memory 19 is read out, and is outputted to the queue through an input port 14', a checking circuit 15' and an output port 18'. |
