发明名称 MEMORY CONTROLLING SYSTEM
摘要 PURPOSE:To realize the use of full space of a bank, by selecting either one of the logic address or the real address given from a map circuit according to the processing conditions of a processor and giving access to memory with the selected address. CONSTITUTION:With an execution program, the bank number set to a bank register BKR is selected by a selector SEL1. And an address within the bank is designated by using a logic address LG-AD sent from an input/output device directly as a real address RL-AD. In case the data is transferred with direct memory access (DMA), an index is carried out for an address conversion map MAP with the upper 4 bits of the logic address (16 bits) to extract a bank (12 bits). The selector SEL1 designates a specific bank by the high-order 4 bits, and the low-order 8 bits are added to an adder ADD to designate a group address GR-AD(L1) within the bank. Furthermore, a segment SG(L2) and a segment address (L3) within each group are designated.
申请公布号 JPS5714932(A) 申请公布日期 1982.01.26
申请号 JP19800088679 申请日期 1980.06.30
申请人 FUJITSU LTD 发明人 HAKAMAZUKA KUNIHIKO;TANAKA TAKAO
分类号 G06F13/12;G06F12/06;G06F12/10 主分类号 G06F13/12
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