| 摘要 |
PURPOSE:To prevent the high-potential level of a memory cell from becoming low by connecting bit lines only to gates of transistors. CONSTITUTION:With clock theta1 high, transistors T9, and T22 to T25 turn on to precharge bit lines BLa and BLb via T22 and T23 and to make BLa and BLb equal in potential. With theta2 high next, transistors T7 and T8 turn on to connect memory cell MC and dummy cell DM to BLa and BLb respectively and at this time, a difference in potential is generated between BLa and BLb. With theta3 high, trnsistors T26, T27, T11, and T12 turn on. Since there is the differnce in potential between BLa and BLb at this time, a difference in potential is generated between points G and F and, in consequence, the state is decided by transistors T13 and T14, so that the potential of a low-level bit line will be lewered by transistors T15 and T16. |
