发明名称 Detection circuit for monitoring the failure of a system to respond in a planned manner to an inputted control signal
摘要 A circuit for detecting the failure of a system to respond in a planned manner to a binary control signal includes a circuit for generating a check signal which normally changes in phase with the control signal. The failure detect circuit includes inverters for generating inverted control and check signals. AND gates compare each signal with the inverted form of the other. A NOR gate produces a failure-indicating signal when an equality is sensed.
申请公布号 US4086530(A) 申请公布日期 1978.04.25
申请号 US19750631167 申请日期 1975.11.11
申请人 PITNEY-BOWES, INC. 发明人 COPPOLA, VINCENT G.;MANDULEY, FLAVIO M.;DLUGOS, DANIEL F.
分类号 G01R31/02;G01R31/28;H02P8/38;(IPC1-7):G01R31/02 主分类号 G01R31/02
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