Return to zero circuit for signal regeneraton - uses four coupled transistor stage to scan input and generate fixed pulse if threshold valve is exceeded

摘要

A return to zero circuit for signal regeneration uses four coupled transistor stages to allow operation over a wide range of frequencies with low power consumption. The outputs of two transistor stages (T2, T4) are connected to a common time to generate an output (Q) and to provide interconnection with two other transistorr stages (T1, T3). The input signal (D) is periodically scanned at the same frequency as the applied clock signal (T) and if the amplitude during this period is higher than a threshold value, then an output (Q) is generated. Immediately following the clock signal going low, if the input is above the threshold, then two transistors (T1, T3) conduct and two (T2, T4) are inhibited. A '1' level is therefore generated on the output line (Q).